In a computer system, a bus may be thought of as the communication interlink between various components of the computer system. Different computer systems may use different types of bus architectures. One type of bus architecture is the Industry Standard Architecture (ISA) bus. Another is the Extended ISA (EISA) bus. A more recent bus architecture is the Peripheral Component Interconnect (PCI) Local Bus architecture. As described by the PCI Local Bus Specification, Revision 2.0 (1993), and Revision 2.1 (1995), the PCI Local Bus is a high performance bus that is intended as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards, and processor.backslash.memory subsystems.
In bus architecture schemes such as PCI, multiple components coupled to the bus must compete for ownership of the bus because only one component can initiate cycles on the bus at a time. Therefore, some mechanism is required to allow each of several components coupled to a bus some amount of access time to that bus in a fair and rational manner. This mechanism is known as arbitration.
A conventional arbitration scheme is described below in reference to FIG. 1. As shown in FIG. 1 an arbiter 10 is coupled to four agents 11 and a target 12. Each of agents A, B, C, and D desire communication with target 12. Arbiter 10 acts as the "traffic cop" determining which of the 4 agents 11 will be granted access to the resources necessary to allow communication with target 12. Arbiter 10 determines which agent will be granted ownership according to a particular algorithm. Arbiter 10 will initiate this algorithm during what is called an arbitration event, and will grant access to the winning agent with the highest priority. Arbiter 10 is designed to prevent any one agent from monopolizing system resources for too long a period of time.
Once the winning agent is granted ownership of the resource, the winning agent executes a transaction during the ensuing period of time after the arbitration event but before the next arbitration event. This period of time is called an arbitration cycle. A transaction executed by the winning agent during an arbitration cycle typically comprises an initial indication of an address, then data associated with that address is read from or written to the target. Multiple pieces of data may be read from or written to the target in a single transaction if each piece of data is associated with consecutive address locations.
After the winning agent has either completed its transaction or arbiter 10 decides that the agent has had enough access time to target 12, arbiter 10 will halt further access to target 12 by that particular agent. Subsequently, arbiter 10 will initiate another arbitration event to determine which of the four agents 11 should next be granted access to the system resources necessary to communicate with target 12.
Each time an agent is granted access to a system resource such as, for example, a bus, a certain amount of leadoff time (access latency) is required to initiate communication with the target before a transaction can be completed. This latency is the result of the time necessary for the target to provide or accept the initial data to or from the bus owner, respectively. However, once an agent has established communication with the target device, multiple transactions may be consecutively executed between that agent and its target device relatively quickly, with minimum overhead. Unfortunately, in conventional arbitration schemes, once an agent has completed execution of a single transaction its ownership of system resources is revoked and the arbiter initiates another arbitration event.
A fragmented access agent is an agent which reads or writes data to non-consecutive regions of target address space, or executes both read and write cycles, or executes some combination of both over the course of communicating with the target. Unfortunately, the conventional arbitration scheme described above can be a significant impediment to fragmented access agents. A conventional arbiter would not treat the agent's communication as a single transaction, as desired by the agent, but rather as a series of transactions. In this manner, the agent's communications are fragmented into multiple transactions executed over a series of arbitration cycles, with each transaction communicating only a fragment of the total data during each cycle. The conventional arbiter initiates one or more arbitration events between each fragment.
As discussed above, a significant amount of overhead time is associated with each arbitration cycle. Therefore, while each successive transaction executed by a fragmented access agent may entail communication of data fragments with the same target device, the speed with which all the data fragments are communicated to or from the target device is significantly slowed by the act of rearbitration between each transaction. In an application in which an agent collects data and the target stores data, such slowing of communication between the agent and the target requires that the agent be equipped with a larger memory buffer for holding the data before it is downloaded to the target device. A larger memory buffer for the agent translates into higher costs for that particular application.